Nvidia has expanded its NVLink Fusion program with NVHBM, a high-bandwidth memory design for companies building semi-custom AI processors. Instead of placing the memory controller on the processor die, NVHBM moves Nvidia’s controller into the base die of the three-dimensional memory stack.
Nvidia says the change can provide up to 30 percent more memory bandwidth, cut HBM power consumption by 15 percent and free as much as 25 percent more area on the processor die compared with standard HBM4E. That reclaimed silicon can be used for compute rather than memory-control circuitry. The company plans a standard implementation supplied by multiple memory partners to reduce integration and qualification work.
Amazon’s Annapurna Labs will be the first announced collaborator to use the technology alongside NVLink Fusion. These figures are Nvidia’s engineering claims, not independent measurements of shipping systems. The practical gains will depend on the final processor, memory supplier and workload, but the design gives custom-chip builders another way to balance compute density, bandwidth and energy use.